1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device which employs a hierarchical word-decode scheme.
2. Description of the Related Art
The hierarchical word-decode scheme employs a hierarchical structure of word lines in which two types of word lines, i.e., main-word lines and sub-word lines, are used for word selection. A typical material used for word lines is polysilicon. Unfortunately, polysilicon has a relatively high resistance for wiring material, causing a significant delay to signals propagating therethrough. A conventional technique to counter this is to establish contact at predetermined intervals between polysilicon word lines and aluminum wiring lines arranged in parallel to the polysilicon word lines, thereby reducing a resistance of the word lines. In order to increase circuit density, however, intervals between the wiring lines needs to be shortened, but it is difficult to implement a pattern of aluminum wiring lines having the same pitch as polysilicon wiring lines. The hierarchical word-decode scheme obviates this problem by dividing polysilicon word lines into sub-word lines having tolerable delays and by using aluminum for main-word lines to achieve sufficiently small delays.
FIG. 1 is an illustrative drawing showing a word-line structure according to a related-art hierarchical word-decode scheme. A main-word decoder 201 decodes a row address to select one of main-word lines 213, and turns the selected main-word line to HIGH. The main-word lines 213 are provided on a wiring layer. In a different wiring layer, four sub-word lines 214 are laid out generally under the main-word lines 213. The sub-word lines 214 are connected to four types of sub-word decoders 209 through 212, respectively. The sub-word decoders of the same type are arranged in a row perpendicular to the extension of the main-word lines 213.
A sub-word-decoder selecting circuit 203 selects one type of sub-word decoder from the four types of the sub-word decoders 209 through 212 via the sub-word-decoder selection lines 215. The selected type of the sub-word decoders connects the main-word lines 213 to the sub-word lines 214. As a result, only one of the four sub-word lines 214 connected to the selected one of the main-word lines 213 becomes HIGH when this sub-word line 214 is selected by the sub-word-decoder selecting circuit 203. This achieves a hierarchical word selection. In the case of data-read operations, for example, data stored in memory-cell arrays 207 is read by sense amplifiers of sense-amplifier blocks 204 only with respect to the selected word.
The memory-cell arrays 207 are arranged in a plurality of column blocks along a column direction (horizontal direction in the figure) as well as in a plurality of row blocks along a row direction (vertical direction in the figure). FIG. 1 only shows a configuration of one row block. This row block is selected when a row-block-selection circuit 202 selectively operates the sense-amplifier blocks 204 of his row block. In general, all the sense-amplifier locks 204 are operated with respect to a selected row lock.
The operation described above is generally referred to as a RAS (row address strobe) operation. Following this RAS operation, a CAS (column address strobe) operation is performed to read data from the semiconductor memory device. That is, a column decoder 217 selectively activates one of the column-selection lines 218 corresponding to an indicated column address so as to select a sense amplifier from one of the sense-amplifier blocks 204, thereby allowing data to be read from the selected sense amplifier.
In semiconductor devices, it is preferable to reduce power consumption as much as possible. In order to meet this demand, a column address may be supplied by the time a row access is performed, so as to allow sense amplifiers to operate only with respect to a column block of a selected column address.
FIG. 2 is an illustrative drawing showing a configuration which activates only a selected column block in the hierarchical word-decode scheme.
In the configuration of FIG. 2, all the sense-amplifier blocks 204 are not driven, but only one of the sense-amplifier blocks 204 is operated with respect 20 to a selected column address. A column-block-selection circuit 208 is provided for this purpose.
Before a row access is performed, a column address is supplied to the device, and the column-block-selection circuit 208 selects a column block corresponding to an indicated column address. Column-block-selection lines 216 extend from the column-block-selection circuit 208, and are connected to sense-amplifier-control circuits 205 and sub-word-decoder-control circuits 206. The sense-amplifier-control circuits 205 drive only one of the sense-amplifier blocks 204 selected by the column-block-selection circuit 208 in a selected row block when the row-block-selection circuit 202 selects this row block. The sub-word-decoder-control circuits 206 supply selection signals from the sub-word-decoder selecting circuit 203 to the sub-word decoders 209 through 212 only in the column block selected by the column-block-selection circuit 208.
In this manner, data access is made to a memory-cell array 207 of a selected column with respect to a selected row block, and one of the sense-amplifier blocks 204 is operated only with respect to the selected column block. This achieves a reduction in the operation load of the circuits relating to the RAS operation, and, at the same time, achieves a reduction in power consumption.
When the RAS operation is performed by the unit of a column block as shown in FIG. 2, however, a speed limit is placed on the CAS operation. In the configuration of FIG. 1, the sub-word lines 214 are selectively activated with respect to all the column blocks, and the sense-amplifier blocks 204 are activated for all the column blocks. As long as successive accesses are made to the same row address, data can be consecutively read from different column addresses of the sense-amplifier blocks 204 by successively selecting the column-selection lines 218. In the configuration of FIG. 2, on the other hand, each time data is read from a column block, a selective activation needs to be performed with respect to the main-word lines 213 and the sub-word lines 214. That is, the RAS operation is necessary at every turn even when the same row address continues to be accessed.
Even though the RAS operation in the configuration of FIG. 2 has a greater speed than the RAS operation of FIG. 1 because of the column-block-wise access, there is a need to carry out the RAS operation each time a column block is accessed. The configuration of FIG. 2 thus suffers a reduction in operation speed when a total of the RAS operation and the CAS operation is taken into consideration, compared to the configuration of FIG. 1.
Accordingly, there is a need for a semiconductor memory device which can achieve a high speed operation while performing column-block-wise access to reduce power consumption.